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1/17 ? semiconductor msm512200/l description the msm512200/l is a 1,048,576-word 2-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm512200/l achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm512200/l is available in a 26/20-pin plastic soj or 26/20-pin plastic tsop. the msm512200l (the low-power version) is specially designed for lower-power applications. features ? 1,048,576-word 2-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (l-version) ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? package options: 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product : msm512200/l-xxsj) 26/20-pin 300 mil plastic tsop (tsopii26/20-p-300-1.27-k) (product : msm512200/l-xxts-k) xx indicates speed rank. product family ? semiconductor msm512200/l 1,048,576-word 2-bit dynamic ram : fast page mode type msm512200/l-70 70 ns 130 ns 150 ns 385 mw 330 mw 5.5 mw/ family access time (max.) cycle time (min.) standby (max.) power dissipation msm512200/l-80 t rac 80 ns 35 ns t aa 40 ns 20 ns t cac 20 ns 20 ns t oea 20 ns msm512200/l-60 60 ns 110 ns 440 mw 30 ns 15 ns 15 ns operating (max.) 0.55 mw (l-version) e2g0017-17-42 this version: jan. 1998 previous version: may 1997
2/17 ? semiconductor msm512200/l pin configuration (top view) 3 4 5 9 10 11 12 13 we ras a9 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cas1 cas2 oe a8 a7 a6 a5 a4 2 dq2 25 nc 1 dq1 26 v ss 26/20-pin plastic soj 3 4 5 9 10 11 12 13 we ras a9 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cas1 cas2 oe a8 a7 a6 a5 a4 2 dq2 25 nc 1 dq1 26 v ss 26/20-pin plastic tsop ( k type ) pin name function a0 - a9 address input ras row address strobe cas1 , cas2 column address strobe dq1, dq2 data input/data output oe output enable we write enable v cc power supply (5 v) nc no connection v ss ground (0 v)
3/17 ? semiconductor msm512200/l block diagram timing generator ras cas1 cas2 timing generator column address buffers internal address counter row address buffers a0 - a9 v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 2 dq1, dq2 2 2 2 2 2 input buffers 2 10 10 10 10
4/17 ? semiconductor msm512200/l electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a9) input capacitance output capacitance (dq1, dq2) c in1 symbol c in2 c i/o 6 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ. ( ras , cas1 , cas2 , we , oe )
5/17 ? semiconductor msm512200/l dc characteristics parameter symbol condition msm512200 /l-60 msm512200 /l-70 msm512200 /l-80 (v cc = 5 v 10%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.5 v ras , cas1 , cas2 average power t rc = min. supply current (operating) ras , cas1 , cas2 = v ih power supply ras , cas1 , cas2 current (standby) ras cycling, average power cas1 , cas2 = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas1 , cas2 = v il , current (standby) dq = enable average power cas1 , cas2 supply current ( cas before ras refresh) ras = v il , average power cas1 , cas2 cycling, supply current t pc = min. (fast page mode) t rc = 125 m s, average power v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 i cc10 cas1 , cas2 supply current (battery backup) 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 2 1 80 5 80 60 200 100 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 70 2 1 70 5 70 55 200 100 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 60 2 1 60 5 60 50 200 100 unit v v m a m a ma ma ma ma ma ma m a m a note 1, 2 1 1, 2 1 1, 2 1, 3 1, 4, 5 1, 5 ras cycling, cycling, before ras before ras , t ras 1 m s notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas1 , cas2 = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/17 ? semiconductor msm512200/l ac characteristics (1/2) parameter random read or write cycle time (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 11, 12 msm512200 /l-60 read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from oe output low impedance time from cas transition time refresh period refresh period (l-version) ras precharge time ras pulse width (fast page mode) ras hold time cas precharge time (fast page mode) cas pulse width ras pulse width cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from cas precharge oe to data output buffer turn-off delay time ras hold time referenced to oe note 4, 5, 6 4, 5 4, 6 4 7 3 5 6 4, 14 7 4 13 13 14 16 ras hold time from cas precharge cas to data output buffer turn-off delay time symbol t rc t rwc t pc t prwc t rac t cac t aa t oea t clz t off t t t ref t ref t rp t ras t rasp t rsh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t cpa t oez t roh t rhcp min. 110 150 40 80 0 0 3 40 60 60 15 10 15 60 5 20 15 0 10 0 15 50 30 0 15 35 max. 60 15 30 15 15 50 16 128 10,000 100,000 10,000 45 30 35 15 unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 130 180 45 95 0 0 3 50 70 70 20 10 20 70 5 20 15 0 10 0 15 55 35 0 20 40 max. 70 20 35 20 20 50 16 128 10,000 100,000 10,000 50 35 40 20 max. 80 20 40 20 20 50 16 128 10,000 100,000 10,000 60 40 45 20 min. 150 200 50 100 0 0 3 60 80 80 20 10 20 80 5 20 15 0 10 0 15 60 40 0 20 45 msm512200 /l-70 msm512200 /l-80
7/17 ? semiconductor msm512200/l ac characteristics (2/2) symbol parameter read command set-up time t rcs read command hold time t rch msm512200 /l-60 read command hold time referenced to ras write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cas lead time data-in set-up time t rrh t wcs t wch t wcr t wp t rwl t cwl t ds data-in hold time t dh data-in hold time from ras t dhr cas to we delay time t cwd column address to we delay time t awd ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) we to ras precharge time ( cas before ras ) we hold time from ras ( cas before ras ) ras to we set-up time (test mode) ras to we hold time (test mode) t rwd t rpc t csr t chr t wrp t wrh t wts t wth oe command hold time t oeh oe to data-in delay time t oed (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 11, 12 cas precharge we delay time t cpwd unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 0 0 0 0 10 45 10 15 15 0 15 50 35 50 80 5 5 10 10 10 10 10 15 15 55 max. min. 0 0 0 0 10 50 10 20 20 0 15 55 45 60 95 5 5 10 10 10 10 10 20 20 65 max. min. 0 0 0 0 10 60 10 20 20 0 15 60 45 65 105 5 5 10 10 10 10 10 20 20 70 max. msm512200 /l-70 msm512200 /l-80 note 8, 13 8 9, 13 9 9 9, 14 9 10, 13 10, 13 13 13 15 13 13 14
8/17 ? semiconductor msm512200/l notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 11. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. the test mode specified in this data sheet is a 2-bit parallel test function. ca0 is not used. in a read cycle, if all internal bits are equal, the dq pin will indicate a high level. if any internal bits are not equal, the dq pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 12. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 13. these parameters are determined by the falling edge of either cas1 or cas2 , whichever is earlier. 14. these parameters are determined by the rising edge of either cas1 or cas2 , whichever is later. 15. t cwl , t dh and t ds should be satisfied by both cas1 and cas2 . 16. t cp is determined by the time both cas1 and cas2 are high.
9/17 ? semiconductor msm512200/l notes concerning cas1 and cas2 control overlap the active-low timings of cas1 and cas2 . skew between cas1 and cas2 is allowed under the following conditions: (1) the timing specification for cas1 and cas2 should be met individually. (2) different operation modes for cas1 / cas2 are not allowed (as shown below). ras cas1 cas2 we delayed write early write (3) closely separated cas1 / cas2 control is not allowed. however, when the condition (t cp t ul ) is satisfied, fast page mode can be performed. ras cas1 cas2 t ul
10/17 ? semiconductor msm512200/l "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t off open t clz valid data-out "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t cwl t rwl timing waveform read cycle write cycle (early write) e2g0094-17-41g
11/17 ? semiconductor msm512200/l read modify write cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
12/17 ? semiconductor msm512200/l fast page mode read cycle fast page mode write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v il C C we v ih v il C C t rasp t rp t ar t crp t rcd t cas t cp t cas t rsh t crp t cas t asr t rah t cah t csh t asc t cah t asc t cah t ral row column column column t rad t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in t dhr note: oe = "h" or "l" v ih t asc t pc t rhcp t cp t cwl t cwl t rwl t cwl t wcr "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rasp t rp t ar t crp t rcd t pc t rsh t crp t cas t cas t cp t cas t rad t asr t rah t asc t cah t csh t asc t cah t asc t cah t ral row column column column t rcs t rch t rcs t rcs t rch t aa t oea t aa t aa t rrh t oea t oea t cac t rac t off t oez t cac t clz t off t oez t cac t clz t oez t off t clz valid data-out valid data-out valid data-out t rhcp t cp t rch t cpa t cpa
13/17 ? semiconductor msm512200/l fast page mode read modify write cycle t wp ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C we v ih v il C C dq v i/oh v i/ol C C t rasp t ar t rp t csh t prwc t rsh t rcd t cas t cp t cas t cp t cas t crp t rad t rah t asr t asc t cah t asc t cah t asc t cah t ral row column column column t rwd t rcs t cwd t cwl t cwd t cwl t cwd t rwl t cwl t awd t awd t awd t oea t wp t oea t wp t oea t aa t oed t cac t ds t dh t cac t aa t rac t ds t dh t cpa t oed t cac t aa t ds t dh t clz t clz t clz out in out out in in t roh t oez t oez t cpa t oed t rcs t rcs t cpwd t cpwd "h" or "l" t oez ras -only refresh cycle ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" open t off
14/17 ? semiconductor msm512200/l ras cas v ih v il C C v ih v il C C column row dq v oh v ol C C we v ih v il C C oe v ih v il C C address v ih v il C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t asc t rah t cah t rcs t ral t rrh t aa t roh t oea t cac t clz t rac t off t oez valid data-out "h" or "l" cas before ras refresh cycle hidden refresh read cycle p q r s \ ] ^ k l m v ih v il ras t rp C C cas v ih v il C C v ih v il we v v t rc t ras t rpc t chr t rp t rpc t cp t csr t wrp t wrh t off t wrp open C C ol oh C C dq note: oe , address = "h" or "l" "h" or "l"
15/17 ? semiconductor msm512200/l hidden refresh write cycle test mode initiate cycle t asr row column v ih v il ras address we cas v ih v il v ih v il v ih v il C C C C C C C C t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral dq v ih v il e e t wcs t chr t ras t wrh t wrp t rc t rp t ar oe v ih v il C C t dhr t ds t wp t wch t dh valid data-in "h" or "l" v ih v il ras cas v ih v il C C C C t ras v oh v ol C C v ih v il C C open t rc t wth t rpc t wts t cp t csr t chr t off note: oe , address = "h" or "l" t rp we dq "h" or "l"
16/17 ? semiconductor msm512200/l (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
17/17 ? semiconductor msm512200/l (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 26/20-p-300-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.38 typ. mirror finish

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